ETP4HPC Webinar - HPC for Urgent Decision-Making

11:00 am to noon CEST

Challenges of more flexible and responsive resource management

This month we have invited the authors of the ETP4HPC White Paper "HPC for Urgent Decision-Making".

Emerging use cases from incident response planning and broad-scope European initiatives (e.g. Destination Earth, European Green Deal and Digital Package) are expected to require federated, distributed infrastructures combining computing and data platforms. These will provide elasticity enabling users to build applications and integrate data for thematic specialisation and decision support, within ever shortening response time windows.

For prompt and, in particular, for urgent decision support, the conventional usage modes of HPC centres is not adequate: these rely on relatively long-term arrangements for time-scheduled exclusive use of HPC resources, and enforce well-established yet time-consuming policies for granting access. In urgent decision support scenarios, managers or members of incident response teams must initiate processing and control the resources required based on their real-time judgement on how a complex situation evolves over time.

In this webinar, Dr. Manolis Marazakis will present this white paper: the technical implications of supporting urgent decisions through establishing flexible usage modes for computing, analytics and AI/ML-based applications using HPC and large, dynamic assets.

A long Q&A session will then allow the audience to exchange with all authors of the white paper.

Speaker

Dr. Manolis Marazakis is a Principal Staff Research Scientist at the FORTH research center in Greece, with a research focus on architectures and efficient systems software for high-performance servers and storage systems. He has contributed to the design, implementation and performance evaluation of several HPC and storage system prototypes, with an emphasis on efficiency and resource management for efficient execution on native and virtualized computing system platforms. His current research interests include systems for combined HPC and data processing workloads, HPC system resilience, and distributed execution platforms for data-driven workflows.

He is currently leading FORTH's system software development for the RISC-V accelerator in the European Processor Initiative (EPI SGA1 and SGA2), and in enhancements to resource management, efficient use of heterogeneous memory devices, and HPC system resilience in the DEEP-SEA project (part of the EuroHPC-01-2019 call). He holds a PhD in Computer Science (granted in 2000 for a thesis in the area of distributed systems), from the University of Crete, Greece. He is a Senior Member of the ACM (with activities related to the SIGOPS, SIGARCH, and SIGHPC special-interest groups), a Senior Member of the IEEE (with participation in the Computer Society), and a Member of the USENIX Technical Society. He is listed as co-inventor in two USPO patents on storage technology.

Links:

CARV systems research laboratory at FORTH: https://www.ics.forth.gr/carv/
Personal page: https://www.linkedin.com/in/mmarazakis/

Panelists

Prof. Dr Dirk Pleiter (professor of high-performance computing at the Division of Computational Science and Technology at the KTH Royal Institute of Technology in Stockholm )

Before joining KTH in 2021, Dirk Pleiter, worked at JSC and as appointed professor at the University of Regensburg from 2011 on. At JSC, he has built up a research team on “Application oriented technology development” and in this role he was involved in various European projects, which mostly focussed on co-design of future HPC architectures and technologies, but also closely worked with different computational science communities. He pursued collaborations with HPC solutions providers, e.g. through the NVIDIA Application Lab at Jülich, which helped to prepare applications for systems like the recently installed JUWELS Booster.

In recent years, his focus was on Arm-based technologies through work with different companies including Arm and Huawei. He also played a leading role in projects working on future HPC-based infrastructures, like PPI4HPC, the first joint procurement of HPC systems in Europe, and Fenix, an effort of various European supercomputing centres to create a federated collection of e-infrastructure services.

Marc Duranton is a member of the Research and Technology Department of CEA (French Atomic Energy Commission). He previously spent more than 23 years in Philips, Philips Semiconductors and NXP Semiconductors.

He has two MSc degrees, in electrical engineering and in computer science, from ENSERG and from ENSIMAG, both in Grenoble and a PhD in signal and image processing from Institut National Polytechnique de Grenoble.

He is currently working on projects related to IoT and High Performance Computing, and on architectures for Neural Network. He worked within Philips Semiconductors in California on several video coprocessors for the VLIW processor TriMedia and for various Nexperia platforms. In NXP Eindhoven (The Netherlands), he led the Ne-XVP project that targeted the design of the hardware and software of a multi-core processor for real-time applications and for consumer video processing. He also led the architecture of the family of L-Neuro chips, digital processors using neural networks techniques. His research interests include parallel and high performance architectures for real-time processing, domain specific architectures, accelerators for Neural-Network models of computation, compiler technology and emerging paradigms for computing systems. He has published several articles and book chapters, and more than 30 patents.