ETP4HPC White Papers

While preparing for the next edition of our Strategic Research Agenda (SRA), ETP4HPC has also opened the process of delivering White Papers, ie. short documents tackling technical issues pertaining to European HPC. The findings of the White Papers will be re-used in the SRA and in others stream of work such as the TransContinuum Initiative

Processing in Memory: the Tipping Point Towards Integrated Hardware/Software Ecosystems for the Edge-Cloud-HPC Continuum Task-Based Performance Portability in HPC < QC | HPC > Quantum for HPC


Processing in Memory: the Tipping Point

Decades after being initially explored in the 1970s, Processing in Memory (PIM) is currently experiencing a renaissance.  By moving part of the computation to the memory devices, PIM addresses a fundamental issue in the design of modern computing systems, the mismatch between the von Neumann architecture and the requirements of important data-centric applications. A number of industrial prototypes and products are under development or already available in the marketplace, and these devices show the potential for cost-effective and energy-efficient acceleration of HPC, AI and data analytics workloads. This paper reviews the reasons for the renewed interest in PIM and surveys industrial prototypes and products, discussing their technological readiness.

Wide adoption of PIM in production, however, depends on our ability to create an ecosystem to drive and coordinate innovations and co-design across the whole stack. European companies and research centres should be involved in all aspects, from technology, hardware, system software and programming environment, to updating of the algorithm and application. In this paper, we identify the main challenges that must be addressed and we provide guidelines to prioritise the research efforts and funding. We aim to help make PIM a reality in production HPC, AI and data analytics.

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Towards Integrated Hardware/Software Ecosystems for the Edge-Cloud-HPC Continuum

Modern use cases such as autonomous vehicles, digital twins, smart buildings and precision agriculture, greatly increase the complexity of application workflows. They typically combine physics-based simulations, analysis of large data volumes and machine learning and require a hybrid execution infrastructure: edge devices create streams of input data, which are processed by data analytics and machine learning applications in the Cloud, and simulations on large, specialised HPC systems provide insights into and prediction of future system state. From these results, additional steps create and communicate output data across the infrastructure levels, and for some use cases, control devices or cyber-physical systems in the real world are controlled (as in the case of smart factories). All of these steps pose different requirements for the best suited execution platforms, and they need to be connected in an efficient and secure way. This assembly is called the Computing Continuum (CC). It raises challenges at multiple levels: at the application level, innovative algorithms are needed to bridge simulations, machine learning  and data-driven analytics; at the middleware level,  adequate tools must enable efficient deployment, scheduling and orchestration of the workflow components across the whole distributed infrastructure;  and, finally, a capable resource management system must allocate a suitable set of components of the infrastructure to run the application workflow, preferably in a dynamic and adaptive way, taking into account the specific capabilities of each component of the underlying heterogeneous infrastructure.

To address the challenges, we foresee an increasing need for integrated software ecosystems which combine current “island” solutions and bridge the gaps between them. These ecosystems must facilitate the full lifecycle of CC use cases, including initial modelling, programming, deployment, execution, optimisation, as well as monitoring and control. It will be important to ensure adequate reproducibility of workflow results and to find ways for creating and managing trust when sharing systems, software and data. All of these will in turn require novel or improved hardware capabilities. This white paper provides an initial discussion of the gaps. Our objective is to accelerate progress in both hardware and software infrastructures to build CC use cases, with the ultimate goals of accelerating scientific discovery, improving timeliness, quality and sustainability of engineering artefacts, and supporting decisions in complex and potentially urgent situations.

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Task-Based Performance Portability in HPC

As HPC hardware continues to evolve and diversify and workloads become more dynamic and complex, applications need to be expressed in a way that facilitates high performance across a range of hardware and situations. The main application code should be platform-independent, malleable and asynchronous with an open, clean, stable and dependable interface between the higher levels of the application, library or programming model and the kernels and software layers tuned for the machine. The platform-independent part should avoid direct references to specific resources and their availability, and instead provide the information needed to optimise behaviour.

This paper summarises how task abstraction, which first appeared in the 1990s and is already mainstream in HPC, should be the basis for a composable and dynamic performance-portable interface. It outlines the innovations that are required in the programming model and runtime layers, and highlights the need for a greater degree of trust among application developers in the ability of the underlying software layers to extract full performance. These steps will help realise the vision for performance portability across current and future architectures and problems.

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< QC | HPC > Quantum for HPC 

Quantum Computing (QC) describes a new way of computing based on the principles of quantum mechanics. From a High Performance Computing (HPC) perspective, QC needs to be integrated: 

  • at a system level, where quantum computer technologies need to be integrated in HPC clusters;
  • at a programming level, where the new disruptive ways of programming devices call for a full hardware-software stack to be built;
  • at an application level, where QC is bound to lead to disruptive changes in the complexity of some applications so that compute-intensive or intractable problems in the HPC domain might become tractable in the future.

The White Paper QC for HPC focuses on the technology integration of QC in HPC clusters, gives an overview of the full hardware-software stack and QC emulators, and highlights promising customised QC algorithms for near-term quantum computers and its impact on HPC applications. In addition to universal quantum computers, we will describe non-universal QC where appropriate. Recent research references will be used to cover the basic concepts. Thetarget audience of this paper is the European HPC community: members of HPC centres, HPC algorithm developers, scientists interested in the co-design for quantum hardware, benchmarking, etc. 

Read online below or download the PDF>

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