ETP4HPC webinar: Emerging Technologies for HPC in Europe - Part 1

11am to noon CEST

In March 2023 at the EuroHPC Summit, ETP4HPC organised a much appreciated session on Emerging Technologies for European HPC. To share it with as many people as possible, we are organising two webinars based on the same content, and with the same presenter pairs.

On 23 June, we will discuss:

• Unconventional HPC architectures: component level, with speakers Tobias Becker (Maxeler) and Robert Haas (IBM Research)
• HPC architectures integration: subsystem/ interposer level, with speakers Craig Prunty (SiPearl) and Marc Duranton (CEA)

A second webinar will be organised on 30 June to cover HPC system  architecture aspects: managing heterogeneity. As usual, the presentations will be followed by a Q&A session which will allow the audience to exchange with the presenters.

Speakers

Tobias Becker VP of Research and Development at Maxeler

Dr. Robert Haas leads one of the technical research departments at IBM Research Europe based in Zurich. His department delivers critical system hardware and software innovation that powers the cloud, AI, server and storage platforms of IBM, as well as leads the race towards in-memory computing. He has an M.Sc. in Communications Systems from EPFL and the Eurécom Institute (Sophia-Antipolis, France), a Ph.D. from ETHZ, and an MBA from Warwick Business School (UK). He has contributed to over 60 patents and several open standards in networking and security.

Craig Prunty, Vice President Marketing & Business Development at SiPearl

Marc Duranton is a member of the Research and Technology Department of CEA (French Atomic Energy Commission). He previously spent more than 23 years in Philips, Philips Semiconductors and NXP Semiconductors.

He has two MSc degrees, in electrical engineering and in computer science, from ENSERG and from ENSIMAG, both in Grenoble and a PhD in signal and image processing from Institut National Polytechnique de Grenoble.

He is currently working on projects related to IoT and High Performance Computing, and on architectures for Neural Network. He worked within Philips Semiconductors in California on several video coprocessors for the VLIW processor TriMedia and for various Nexperia platforms. In NXP Eindhoven (The Netherlands), he led the Ne-XVP project that targeted the design of the hardware and software of a multi-core processor for real-time applications and for consumer video processing. He also led the architecture of the family of L-Neuro chips, digital processors using neural networks techniques. His research interests include parallel and high performance architectures for real-time processing, domain specific architectures, accelerators for Neural-Network models of computation, compiler technology and emerging paradigms for computing systems. He has published several articles and book chapters, and more than 30 patents.

A few pictures from the live session at the EuroHPC Summit: