Exploiting the Potential of European HPC Stakeholders in Extreme-scale Demonstrators

18th May 2017, 2-7pm,  Barcelona, Catalunya @ European HPC Summit Week, Sala Auditori (UPC Campus Nord, Building: Vertex)

within the European HPC Summit Week


ETP4HPC, the European HPC Technology Platform, would like to continue the development of its Extreme-scale Demonstrators (EsDs) concept through a discussion involving all European HPC stakeholders. The concept of European HPC system prototypes has been proposed by ETP4HPC and it is available at: The EsDs are research projects aimed at integrating European HPC Technology and Application expertise into fully operational world-class HPC systems. This concept is included in our current EC Work Programme 2018-20 draft and forms the core of the further development of HPC technology in Europe.

The European Technology (FETHPC and other FP) projects, application owners (EXDCI WP3), the Centres of Excellence in Computing Applications (CoEs), technology providers, HPC centres/PRACE and  HPC System Integrators will play a pivotal role in this process.

The objective of this peer-to-peer Round-table workshop is to allow ALL STAKEHOLDERS to familiarise themselves with the potential of the European HPC Ecosystem on an equal basis with a view to setting up consortia leading to successful EsD projects. It will provide an opportunity for a level set and discussion before the EsD concept's publication in a WP18-20 call in autumn this year. Representatives of various stakeholder groups (FETHPC projects, application owners (EXDCI WP3), CoEs, integrators, technology providers, HPC centres/PRACE) participating in future EsD projects will have a chance to update one another and jointly develop a position regarding a set of critical project implementation aspects. Most importantly, the FETHPC projects currently under way should share their most likely contributions to the EsD projects. We expect each of the participating FETHPC projects, application owners (EXDCI WP3), CoEs, integrator companies, technology providers and HPC Centres/PRACE to send only ONE representative each.  

This workshop is organised by ETP4HPC on behalf of EXDCI within the European HPC Summit Week:

The agenda of the workshop will include: 1/ a presentation of the EsD Concept and 2/ presentations of European HPC Projects and their potential contributions to EsD projects (moderated by a panel consisting of representatives of the main stakeholders of European HPC):

  • 1400-1415 - Welcome and Introduction - Michael Malms and Marcin Ostasz, ETP4HPC
  • 1415 - 1450 - EsD Concept and latest updates - Thomas Eickermann (Juelich SC - ETP4HPC)
  • 1450 - 1510 - Top-down system design approach - Hans-Christian Hoppe (Intel - ETP4HPC)
  • 1510 - 1530 - Applications as drivers - Erwin Laure (KTH - ETP4HPC)
  • 1530 - 1630 - The Projects' Contrubutions to EsDs (1) - THE HPC TECHNOLOGY PROJECTS (less than 8 minutes each)
  • 1630 - 1700 - BREAK
  • 1700 - 1745 - The Projects' Contrubutions to EsDs (2) - THE HPC TECHNOLOGY PROJECTS ((less than 8 minutes each)
  • 1745 - 1830 - Panel Discussion and Q&As - Panel: Laurent Cargmel (ATOS - a technology provider), Erik Lindahl (KTH - an application owner), Dirk Pleiter (Juelich SC - a HPC Centre), Mike Dewar (NAG - an SME).

These are the general presentations used at the Workshop: Agenda, EsD Concept Update, Top-down system design approachApplications (CoEs)

These are the European HPC Technology Project presentations shown at the workshop (in the order of appearance):

FP 7 Projects: DEEP Projects, Mont-Blanc 3, Human Brain Project PCP and PRACE 3IP PCP

Horizon 2020 Projects: AllScale, ComPat, ECOSCALE, ESCAPE, ExaHyPE, ExaNeSt, ExaNoDe, INTERTWinE, Mango, NextGenIO, SAGE

These are the contributions provided by various European HPC technology projects: AllScale, ComPat, Deep Projects, ECOSCALE,  ESCAPE, ExaHyPE, ExaNeSt, ExaNoDe, Human Brain Project PCP, INTERTWinE, Mango, Mont-Blanc 3, NextGenIO, SAGE, ...

These are the questions the HPC technology projects are expected to answer.

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