RIAG
The Research and Innovation Advisory Group (RIAG) is a component of the EuroHPC JU's Industrial and Scientific Advisory Board, which provides independent advice to the Governing Board on the strategic research and innovation agenda and on the acquisition and operation of the supercomputers owned by the Joint Undertaking.
The RIAG is composed of 12 members, six of which are appointed by the Private Members (i.e. ETP4HPC, BDVA and QuiC) and the other six are appointed by the Governing Board. 12 observers are appointed similarly. Their term of office is two years, and can be renewed once.
The RIAG draws up and regularly update the draft multiannual strategic research and innovation agenda. This draft multiannual strategic research and innovation agenda identifies research and innovation priorities for the development and adoption of technologies and key competences for High-Performance Computing across different application areas in order to support the development of an integrated High-Performance Computing ecosystem in the EU, strengthen competitiveness and help create new markets and societal applications.
ETP4HPC in the RIAG
ETP4HPC has three members in the RIAG, as well as four observers. Together they represent the interests of our association in the EuroHPC RIAG.
Meet our RIAG team!
Breaking news: new ETP4HPC representatives elected!
On 13 February 2024, as the term of office of RIAG members was coming to its end, the ETP4HPC Steering Board elected new representatives to the RIAG:
Members:
- Daniele Cesarini (CINECA)
- Maike Gilliot (CEA) - new member of RIAG
- Hans-Christian Hoppe (ParTec AG) - new member of RIAG
Observers:
- Rémi Barbarin (Bull / Eviden) - new observer
- Valeria Bartsch (Fraunhofer) - new observer
- Martin Palkovic (ECMWF)
- Craig Prunty (SiPearl) - new observer
Members
Dr Daniele Cesarini, CINECA, member of the ETP4HPC Steering Board.
Daniele Cesarini graduated in Computer Engineering from the University of Bologna (Italy) in 2014, where he also earned his Ph.D. in Electronics, Telecommunications, and Information Technologies Engineering in 2019.
He is currently an HPC Specialist at Cineca High Performance Computing department where he works in the area of performance optimization and evaluation of next-generation HPC architectures to improve the roadmap of CINECA’s HPC infrastructures. His range of expertise include parallel programming model, shared and distributed memory systems, high-performance computer architectures and runtime systems. His research interests also concern the development of SW-HW co-design strategies as well as algorithms for parallel programming support for energy efficient HPC systems. He has also an active role in the energy efficient HPC activities of CINECA where his work is focused to improve the power efficiency of the CINECA's datacenter.
Maike Gilliot, CEA
Maike Gilliot graduated from TU Darmstadt (Germany) at the department of Computer Science. She worked as research assistant at the University of Freiburg at the department of Telematics, before joining Inria (France) in 2011. At Inria, she worked as a technology transfer officer at the Inria Research Center of Saclay-Île-de-France. In February 2016, she joined the Teratec association to manage its European collaborations with academic and industrial partners and contribute to different EU-funded research projects. She joined the ETP4HPC office team at the same time, first to take care of start-up and SME development, and as of 2018 as the ETP4HPC Office manager. Since 2021, she is EU project manager at CEA for HPC-related projects.
Hans-Christian Hoppe, ParTec AG
Hans-Christian Hoppe has made significant contributions to HPC since the 1990s, with an impact on the MPI standard, first proof use of virtualization in Grid systems, a leading scalable performance analysis tool, and the co-definition of the Modular Supercomputing Architecture (MSA).
From 2003, he worked as a Principal Engineer with Intel, responsible for the Intel Cluster tools, early research on Manycore, the Intel Visual Computing Institute, and the Intel Exascale Lab at JSC, and as co-lead for a Darpa project on disruptive Graph-analytics architectures.
In 2022, he joined Jülich Supercomputing Centre and ParTec AG, leading the DEEP-SEA project and contributing to several other EU-funded projects, including the RAISE CoE and EUPEX. His research interests include heterogeneous system architectures, dynamic use of resources in HPC, scalable performance analysis methods and tools, and integration of disruptive technologies (such as Quantum Computing) into HPC infrastructures.
Observers
Rémi Barbarin, Bull SAS (Eviden group)
Head of AI, Software R&D
Dr Valeria Bartsch, Fraunhofer
Dr. Valeria Bartsch is part of the management team of the High Performance Computing department at the Fraunhofer Institute for Industrial Mathematics (ITWM) and leads a team in the areas of Next Generation Computing / Quantum Computing. She received her Diploma in Physics at the University of Dortmund (2000) and her PhD degree from the University of Karlsruhe (2003). Several postdoctoral positions in the area of experimental particle physics followed. A growing interest in computing led to the current position.
Dr Martin Palkovic, ECMWF, member of the ETP4HPC Steering Board
Martin Palkovic is Director of Computing at European Centre for Medium-Range Weather Forecasts (ECMWF) since 2018. He is responsible among others also for the BOND programme consisting of build of ECMWF new datacentre in Bologna, installation of 4 HPC complexes with overall performance over 36 PFLOPS and moving the DHS (close to ½ EByte of data) from current datacentre in Reading, UK to Bologna, Italy.
He was born in Bratislava, Slovakia and has M.Sc. degree in Electrical Engineering (processor design) from the Slovak University of Technology, M.Sc. degree in Economics (international trade) from the University of Economics in Bratislava and Ph.D. in Electrical Engineering (compiler optimisations/loop transformations) from Technische Universiteit Eindhoven. He joined imec Leuven, Belgium in 2001, where he has been a researcher from 2001 to 2008 and senior researcher from 2008 to 2012 working on high-level optimizations and parallel platform architectures for low power. From 2012 to 2017 Dr. Palkovic was the director of newly established IT4Innovations, the national supercomputing center in Czech Republic. Under his leadership, the Czech national supercomputing centre was established with #40 system in Top500 and strong international reputation was gained. He undertook also the first steps so that Czech Republic joined EuroHPC at the beginning of 2018. During 2018 he was for a short period the vicepresident of engineering at Codasip, the RISC-V IP company in the Czech Republic. He is author and co-author of more than 50 publications in the embedded system domain and was the general chair of HiPEAC 2016 in Prague and a member of the Horizon 2020 Future and Emerging Technologies Advisory Group. He is the member of ESFRI Strategy Working Group on Data, Computing and Digital Research Infrastructure as well as other advisory bodies (e.g. EPI, Intel EMEA HPC AI Advisory Council).
Craig Prunty, SiPearl, member of the ETP4HPC Steering Board
Vice President Marketing & Business Development at SiPearl
A business development and product marketing expert in the global high-performance computing (HPC) market, Craig Prunty has spent the majority of his career in France and California with global semiconductor companies (Marvell Semiconductor, Cavium, AppliedMicro), contributing to the commercial success of several product lines. In his various positions, he has been engaged in industry consortiums and has built up a robust global network of partners.
Prior to moving to SiPearl, Craig was Marketing Director for Marvell Semiconductor’s server processors division in Santa Clara, California. He has successfully developed new markets including high-performance computing harnessing Arm technology.
A dual French and American national, Craig has a Master in Electrical Engineering from San Diego State University.
